1. Field of the Invention
The present invention relates to a semiconductor memory device and semiconductor device and, for example, to a volatile semiconductor memory device having an SRAM cell.
2. Description of the Related Art
The mainstream memory cell of a current static random access memory (SRAM) is a CMOS-type 6T cell having six MOS transistors. This cell is formed from a flip-flop including two CMOS inverters, and two transfer gates that connect the two nodes of the flip-flop to a bit line pair. As a characteristic feature, an SRAM can stably maintain data because it statically stores data by using a flip-flop (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-164445).
However, as the element size decreases aiming at improving the performance of an large-scale integrated circuit (LSI) and increasing the number of mounted elements, scaling of the power supply voltage also progresses. Along with the size reduction, a threshold voltage Vth of a transistor, which should be controlled to a given value, varies between elements remarkably.
Static noise margin (SNM) is an index representing the operation margin of an SRAM. The SNM is a voltage margin during operation and is well known as a so-called butterfly curve of an SRAM cell, which superimposes the input/output characteristics of two inverters included in a flip-flop when a word line of a given cell is selected, i.e., the transistor of its transfer gate is ON. Even when the input/output characteristic shifts due to noise, there is a margin corresponding to the SNM before the butterfly curve distorts to destroy data. The larger the SNM is, the more stable the data maintain characteristic of a cell is. Unlike a normal inverter characteristic, when a word line is turned on, the potential on the low (“L”) level side is raised by the level (normally high (“H”) level) of a bit line connected through a transfer gate to an intermediate potential determined by the drive power ratio of the transfer gate to a driver (NMOS transistor included in the inverter).
As described above, scaling of the power supply voltage causes scaling of the entire butterfly curve so that the SNM becomes small, as a matter of course. Additionally, when the threshold voltage Vth varies, the characteristics of the two inverters included in the flip-flop shift from each other. This makes the butterfly curve asymmetric. The smaller characteristic determines the SNM of the SRAM cell. If scaling of the power supply voltage progresses, and the threshold voltage Vth varies to a certain extent or more with a distribution, no SNM is ensured. That is, cells having no butterfly curve exist stochastically. The probability rises as the capacity of the SRAM increases, i.e., the number of SRAM cells increases. The word line of such a cell is in a selected state. Changing the transfer gate to the ON state alone may destroy stored data. Hence, the memory cannot normally operate.
An SRAM can employ various kinds of array architectures. A compilable SRAM capable of flexibly changing the number of bits and structure generally employs an array architecture that forms a cluster corresponding to each I/O to ensure the degree of freedom of the I/O width from the viewpoint of the area efficiency, speed, and power. In this case, when a row is selected, a cell at the cross-point between that row and a column selected for each I/O is actually selected and accessed to write or read data. Cells connected to the same row of the selected cell and unselected columns need to maintain data without read or write, although the word lines are turned on. Assume that these cells include the above-described cell without SNM. In write, new data is written in the selected cell connected to the selected column so data destruction does not occur. However, all cells connected to unselected columns with word lines in the ON state may cause data destruction. In read, all cells connected to the selected row and having word lines in the ON state may cause data destruction independently of the selected/unselected state of the columns.